1. Field of the Invention
The present invention generally relates to an interconnection structure of a semiconductor device and a method of manufacturing the same, and more particularly, to an interconnection structure of a semiconductor device having a local interconnection structure for implementing miniaturization of the device, and a method of manufacturing the same.
2. Description of the Background Art
Recently, high speed operation and miniaturization of a semiconductor device have been more required. In order to satisfy these requirements, an interconnection structure used in the semiconductor device employs a so-called local interconnection structure, or the resistance of a conductive layer is reduced by introducing a silicide layer as a part of the conductive layer.
Description will now be given of a semiconductor device having a conventional local interconnection structure with reference to FIG. 28.
A gate electrode 4 is formed on the main surface of a silicon substrate 1 with a gate oxide film 10 interposed therebetween. A silicide film 5 for reducing the resistance of gate electrode 4 is formed on gate electrode 4. The sidewall of gate electrode 4 and silicide film 5 is covered with a sidewall oxide film 6.
Active regions 2a, 2b forming a source/drain region are formed a prescribed depth from the main surface of silicon substrate 1. Silicide layers 3a, 3b for implementing low resistance of active regions 2a, 2b are formed on the main surfaces of active regions 2a, 2b.
Here, a local interconnection of a titanium layer 7 and a titanium nitride layer 8 is formed, so that gate electrode 4 and active region 2a are connected. Gate electrode 4, titanium layer 7, and titanium nitride layer 8 are covered with an interlayer oxide film 9.
Description will now be given of the manufacturing process of a semiconductor device having the above described local interconnection structure.
Referring to FIG. 29, gate electrode 4 of polysilicon or the like having a prescribed shape is formed on silicon substrate 1 with gate oxide film 10 of a silicon oxide film or the like interposed therebetween. Then, with gate electrode 4 used as a mask, impurities are introduced into silicon substrate 1 to form active regions 2a, 2b.
Then, referring to FIG. 30, a silicon oxide film or the like is deposited a prescribed thickness on silicon substrate 1. By anisotropically etching the silicon oxide film, sidewall oxide film 6 is formed on the sidewall of gate electrode 4.
Referring to FIG. 31, a Co film or Ti film 3 is deposited on the surface of silicon substrate 1 with a sputtering method. Then, the film is subjected to lamp annealing, so that silicide film 5 and silicide layers 3a, 3b are formed on gate electrode 4 and active regions 2a, 2b, as shown in FIG. 32.
Referring to FIG. 33, titanium layer 7 and titanium nitride layer 8 are deposited on the entire surface of silicon substrate 1 with a sputtering method. Then, referring to FIG. 34, a resist film 12 with a prescribed pattern shape is formed on titanium nitride layer 8. With resist film 12 used as a mask, titanium nitride layer 8 and titanium layer 7 are etched. After removing resist film 12, an interlayer oxide film 9 is deposited on the entire surface of silicon substrate 1, whereby a semiconductor device having such a local interconnection structure as shown in FIG. 29 is complete.
The above described local interconnection structure of a semiconductor device has, however, the following problems.
First, in the step of patterning titanium layer 7 and titanium nitride layer 8 shown in FIGS. 33 and 34, silicide film 5 and silicide layer 3b formed on gate electrode 4 and active region 2b are similarly etched by an etchant used in etching titanium layer 7 and titanium nitride layer 8. Therefore, in order to pattern titanium layer 7 and titanium nitride layer 8 favorably on silicide film 5 and silicide layer 3b, as shown in FIG. 34, a very difficult step is required.
In order to facilitate the patterning step, titanium layer 7 and titanium nitride layer 8 must be decreased in thickness as much as possible. However, titanium layer 7 and titanium nitride layer 8 reduced in thickness cause the resistance value of the local interconnection to increase, affecting operation of the semiconductor device unfavorably.